Semiconductor Device and Method for Manufacturing a Semiconductor Device

ABSTRACT

According to an embodiment, a method for manufacturing a semiconductor device is provided. The method includes providing a mask layer which is used as an implantation mask when forming a doping region and which is used as an etching mask when forming an opening and a contact element formed in the opening. The contact element is in contact with the doping region.

FIELD OF THE INVENTION

The embodiments described herein relate to semiconductor devices, andmore particularly to semiconductor devices having a doping regionaligned with respect to a contact element in electrical contact with thedoping region and methods of manufacturing the same.

BACKGROUND

Semiconductor devices such as bipolar transistors are used for manyapplications. Bipolar transistors often have insufficient emitterefficiency due to process variations. For example, lateral misalignmentbetween the emitter contact and the emitter results in a reduction ofthe lateral emitter width which can lead to an increased recombinationrate at the emitter contact. The closer the emitter contact is to anedge of the emitter, the higher the recombination rate. A highrecombination rate also deteriorates the emitter efficiency and reducesthe gain of the bipolar transistor. Furthermore, other transistorparameters can also vary. Typically, laborious design rules are requiredin an attempt to compensate these effects, for example by increasing theused chip area which also increases the production costs.

SUMMARY

According to one embodiment, a method for manufacturing a semiconductordevice is provided. The method includes providing a semiconductorsubstrate comprising a first surface; forming a first insulating layeron the first surface of the semiconductor substrate; forming a masklayer having a first opening on the first insulating layer, the firstopening of the mask layer defining a location of a first doping region;performing a first implantation step using the mask layer asimplantation mask to form the first doping region in the semiconductorsubstrate; etching the first insulating layer selectively with respectto the mask layer to expose a portion of the first doping region byforming a first opening in the first insulating layer using the masklayer as etching mask; forming a second insulating layer on the masklayer to cover the first opening in the mask layer, the material of thefirst and second insulating layers being selectively etchable withrespect to the material of the mask layer; forming an etching mask onthe second insulating layer for defining at least a first opening in thesecond insulating layer above the first opening of the mask layer;etching the second insulating layer selectively with respect to theetching mask and the mask layer to form the first opening in the secondinsulating layer, the first opening of the second insulating layerexposing the first opening in the mask layer; and depositing aconductive material to form at least one contact element disposed in thefirst opening formed in the first insulating layer, the first openingformed in the second insulating layer and the first opening formed inthe mask layer, the contact element being in contact with the firstdoping region and the mask layer.

According to one embodiment, a semiconductor device is provided. Thesemiconductor device includes a semiconductor substrate having a firstsurface and a first doping region. A first insulating layer having afirst opening is disposed on the first surface of the semiconductorsubstrate, the first opening being arranged above the first dopingregion. A mask layer on the first insulating layer includes a firstopening. The first opening in the first insulating layer and the firstopening in the mask layer are laterally centred with respect to thefirst doping region. A second insulating layer on the mask layerincludes a first opening above the first opening of the mask layer. Atleast a first contact element is arranged in the first opening of thesecond insulating layer, the first opening of the mask layer and thefirst opening of the first insulating layer. The first contact elementelectrically connects the first doping region with the mask layer.

According to one embodiment, a method for manufacturing a semiconductordevice is provided. The method includes providing a semiconductorsubstrate having a first surface, a first doping region and a seconddoping region laterally spaced to the first doping region, a firstinsulating layer on the first surface of the semiconductor substrate,and a conductive mask layer having at least a first opening and a secondopening spaced apart from the first opening on the first insulatinglayer, the first opening of the conductive mask layer being arrangedabove the first doping region and the second opening of the conductivemask layer being arranged above the second doping region; forming asecond insulating layer on the conductive mask layer to cover the firstand second openings in the conductive mask layer, the material of thefirst and second insulating layers being selectively etchable withrespect to the material of the conductive mask layer; forming an etchingmask on the second insulating layer for defining a first opening and asecond opening of the second insulating layer; etching the secondinsulating layer selectively with respect to the etching mask and theconductive mask layer to form the first opening and the second openingof the second insulating layer, the first opening of the secondinsulating layer exposing the first opening in the conductive masklayer, the second opening of the second insulating layer exposing thesecond opening in the conductive mask layer; etching the firstinsulating layer using the conductive mask layer as etching mask to forma first and a second opening in the first insulating layer for exposingat least a respective portion of the first and second doping region; anddepositing a conductive material to form a first contact elementdisposed in the first opening formed in the first insulating layer, thefirst opening formed in the second insulating layer and the firstopening formed in the conductive mask layer, and a second contactelement disposed in the second opening formed in the first insulatinglayer, the second opening formed in the second insulating layer and thesecond opening formed in the conductive mask layer, the first contactelement being in electrical contact with the first doping region and theconductive mask layer, and the second contact element being inelectrical contact with the second doping region and the conductive masklayer.

According to one embodiment, a semiconductor device is provided. Thesemiconductor device includes a semiconductor substrate having a firstsurface, a first doping region and a second doping region laterallyspaced apart from the first doping region. A first insulating layer isarranged on the first surface of the semiconductor substrate andincludes a first opening and a second opening. A conductive mask layeron the first insulating layer has a first opening and a second opening.The first opening of the conductive mask layer is arranged above thefirst opening of the first insulating layer and the second opening ofthe conductive mask layer is arranged above the second opening of thefirst insulating layer. A second insulating layer on the conductive masklayer has a first opening and a second opening. The first opening of thesecond insulating layer is arranged above the first opening of theconductive mask layer, and the second opening of the second insulatinglayer is arranged above the second opening of the conductive mask layer.A first contact element is disposed in the first opening of the firstinsulating layer, the first opening of the conductive mask layer and thefirst opening of the second insulating layer, and a second contactelement is disposed in the second opening of the first insulating layer,the second opening of the conductive mask layer and the second openingof the second insulating layer. The first contact element is inelectrical contact with the first doping region and with the conductivemask layer, and the second contact element is in electrical contact withthe second doping region and with the conductive mask layer.

According to one embodiment, a semiconductor device is provided. Thesemiconductor device includes a semiconductor substrate having a firstsurface, a doping area of a first conductivity type, a first dopingregion of the second conductivity type arranged in the doping area ofthe semiconductor substrate, and a contact doping region of the secondconductivity type arranged in the first doping region at the firstsurface. The contact doping region has a higher doping concentrationthan the first doping region. A first insulating layer is on the firstsurface of the semiconductor substrate. The first insulating layerincludes a first opening above the contact doping region. A mask layeron the first insulating layer includes a first opening. The firstopening in the first insulating layer and the first opening in the masklayer are laterally centred with respect to the contact doping region. Asecond insulating layer on the mask layer includes a first opening abovethe first opening of the mask layer. At least one contact element isarranged in the first opening of the second insulating layer, in thefirst opening of the mask layer and in the first opening of the firstinsulating layer. The contact element electrically connects the contactdoping region with the mask layer.

Those skilled in the art will recognize additional features andadvantages upon reading the following detailed description, and uponviewing the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The components in the figures are not necessarily to scale, insteademphasis being placed upon illustrating the principles of the invention.Moreover, in the figures, like reference numerals designatecorresponding parts. In the drawings:

FIGS. 1A to 1C illustrate processes of a method for manufacturing asemiconductor device according to one embodiment;

FIGS. 2A to 2C illustrate the design of lateral bipolar transistorsaccording to several embodiments;

FIG. 3A to 3F illustrate processes of a method for manufacturing asemiconductor device according to one embodiment;

FIGS. 4A to 4C illustrate processes of a method for manufacturing asemiconductor device according to one embodiment;

FIG. 5 illustrates the layout of an electrical connection according toan embodiment;

FIG. 6 illustrates a semiconductor device having two lateral bipolartransistors according to an embodiment;

FIG. 7 illustrates a semiconductor device having two lateral bipolartransistors with a local wiring according to an embodiment; and

FIG. 8 illustrates a semiconductor device having a lateral bipolartransistor according to an embodiment.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which are shownby way of illustration specific embodiments in which the invention maybe practiced. In this regard, directional terminology, such as “top”,“bottom”, “front”, “back”, leading”, “trailing” etc., is used withreference to the orientation of the Figure(s) being described. Becausecomponents of embodiments can be positioned in a number of differentorientations, the directional terminology is used for purpose ofillustration and is in no way limiting. Other embodiments may beutilised and structural or logical changes may be made without departingfrom the scope of the present invention. The following detaileddescription, therefore, is not to be taken in a limiting sense, and thescope of the present invention is defined by the appended claims. Theembodiments being described use specific language, which should not beconstrued as limiting the scope of the appended claims.

Features of the various exemplary embodiments described herein may becombined with each other, unless specifically noted otherwise. Forexample, features illustrated or described as part of one embodiment canbe used in conjunction with features of other embodiments to yield yet afurther embodiment. It is intended that the present description includessuch modifications and variations.

The term “lateral” as used in this specification intends to describe anorientation parallel to the main surface of a semiconductor substrate.

The term “vertical” as used in this specification intends to describe anorientation, which is arranged perpendicular to the main surface of thesemiconductor substrate.

In this specification, a second surface of a semiconductor substrate isconsidered to be formed by the lower or back-side surface while a firstsurface is considered to be formed by the upper, front or main surfaceof the semiconductor substrate. The terms “above” and “below” as used inthis specification therefore describe a relative location of astructural feature to another structural feature with consideration ofthis orientation.

When referring to semiconductor devices, at least two-terminal devicesare meant, an example is a diode. Semiconductor devices can also bethree-terminal devices such as a bipolar transistor or a field-effecttransistor (FET), insulated gate bipolar transistor (IGBT), junctionfield effect transistors (JFET), and thyristors to name a few. Thesemiconductor devices can also include more than three terminals.According to an embodiment, semiconductor devices are power devices.Integrated circuits include a plurality of integrated devices.

The terms “electrically connected” and “electrical connection” intendsto describe that there is an ohmic contact between to elements orstructures.

Specific embodiments described herein pertain to, without being limitedthereto, semiconductor devices with at least one, typically with two ormore bipolar transistors.

With reference to FIGS. 1A to 1C, a first embodiment of a method formanufacturing a semiconductor device is described. A semiconductorsubstrate or wafer 10 is provided having a first surface 11 and a secondsurface 12 arranged opposite the first surface 11. The semiconductorsubstrate or wafer 10 can be made of any semiconductor material suitablefor manufacturing semiconductor devices. Examples of such materialsinclude, without being limited thereto, elementary semiconductormaterials such as silicon (Si), group IV compound semiconductormaterials such as silicon carbide (SiC) or silicon germanium (SiGe),binary, ternary or quaternary III-V semiconductor materials such asgallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide(InP), gallium nitride (GaN), aluminium gallium nitride (AlGaN), indiumgallium phosphide (InGaPa) or indium gallium arsenide

The semiconductor substrate 10 can include an n-doped doping area.Semiconductor substrate 10 can also be formed by an n-doped epitaxiallayer formed on a p-doped wafer. For the purpose of illustration and notmeant as limitation, n-type is referred to as first doping type whilep-type is referred to as second doping type. A skilled person willappreciate that reverse doping conditions can also be applied. For thepurpose of illustration in this embodiment, semiconductor substrate 10is n-doped.

A first insulating layer 31 is formed on the first surface 11 of thesemiconductor substrate 10, for example by thermal oxidation ordeposition. A mask layer 40 is formed on the first insulating layer 31.Mask layer 40 includes at least one opening 41, which is referred to asfirst opening 41. First opening 41 can be formed by using a photo mask(not shown). Mask layer 40 can be a hard mask layer. According to anembodiment, mask layer 40 can be comprised of an electrically conductivematerial. Examples are polysilicon and chromium silicide (CrSi₂). Masklayer 40 can be a polysilicon field plate which is used in other regionsof semiconductor device as field plate, for example in lateraltermination structures. According to an embodiment, mask layer 40 can bycomprised of a dielectric material.

First insulating layer 31 can be comprised of a material which can beetched selectively with respect to the mask layer 40.

Mask layer 40 is used for forming a first doping region 21 of secondconductivity type, which is p-doped in this embodiment. Mask layer 40 isused as implantation mask with opening 41 defining the location of thefirst doping region 21. Dopants can be implanted through firstinsulating layer 31 which will serve as scatter oxide to preventchannelling during implantation. Alternatively, implantation can be donewithout first insulating layer 31 which can be etched selectively withrespect to mask layer 40 to expose the first surface 11 of thesemiconductor substrate 10 before implantation.

The implantation process can be carried out such that substantially nodopants penetrate mask layer 40. Hence, implantation into thesemiconductor substrate 10 occurs only in the region of the firstopening 41. To this end, the implantation energy can be appropriatelyselected. Implantation of dopants using mask layer 40 as implantationmask results in the formation of the first doping region 21 in aself-aligned manner with respect to the first opening 41 of mask layer40.

First doping region 21 can be annealed which typically results in afurther diffusion of the implanted dopants into the semiconductorsubstrate 10. Furthermore, implantation damages are annealed. Theresulting structure is illustrated in FIG. 1A showing the first dopingregion 21 self-aligned, i.e. centred with respect to the opening 41 ofmask layer 40.

The term self-aligned intends to describe that the structures arelaterally aligned with respect to each other. Particularly, thestructures are laterally centred with respect to each other. FIG. 1Ashows that the centre of the first doping region 21 is on the samevertical line as the centre of the first opening 41 when seen in avertical cross-section. The lateral distance between a first outer edgeof the first doping region 21 to a first edge of the first opening 41 isthe same as the lateral distance between a second outer edge of thefirst doping region 21 to a second edge of the first opening 41 whenseen in the vertical cross-section. The respective lateral distances areillustrated by arrows in FIG. 1A. In a plan view onto the first surfaceof the semiconductor substrate, first doping region 21 also appearscentred with respect to first opening 41 of mask layer 40.

In a further process, a second insulating layer 32 is formed on the masklayer 40 to cover the first opening 41 of the mask layer 40. Secondinsulating layer 32 can be comprised of a material which can be etchedselectively with respect to the mask layer 40. For example, secondinsulating layer 32 can be comprised of the same material as firstinsulating layer 31. First and second insulating layers 31, 32 can bemade of silicon oxide, for example.

An etching mask 33, for example a resist mask, is formed on the secondinsulating layer 32. Etching mask 33 includes an opening 33 a whichdefines the location of a first opening 32 a to be formed in the secondinsulating layer 32. The opening 33 a of etching mask 33 is arrangedabove the first opening 41 of the mask layer 40 and has a lateralextension which is larger than the lateral extension of the firstopening 41 of the mask layer 40 to ensure that the first opening 41 inthe mask layer 40 becomes fully exposed.

As opening 33 a of the etching mask 33 is larger than the first opening41 of mask layer 40, misalignment of etching mask 33 with respect tomask layer 40 is uncritical. To ensure that first opening 41 of masklayer 40 is fully covered by opening 33 a of etching mask 33 when seenin a projection onto the first surface 11 of the semiconductor substrate10, the size of opening 33 a of etching mask 33 should take account ofpossible misalignment tolerances. The subsequently formed first opening32 a of second insulating mask 32 has therefore a lateral extensionwhich is larger than the lateral extension of first opening 41 in themask layer 40 and completely exposes first opening 41 of mask layer 40.

The first opening 32 a of the second insulating layer 32 is formed usingan etching process, which can be selective with respect to the materialof the mask layer 40 and the material of the etching mask 33. FIG. 1Billustrates an intermediate stage during etching. The etching results ina removal of the material of the second insulating layer 32 within theregion defined by opening 33 a of the etching mask 33. Since opening 33a is larger than opening 41 of mask layer 40, portions of mask layer 40arranged adjacent to first opening 41 are also exposed, i.e. firstopening 41 of mask layer 40 is completely exposed. The etching alsoresults in the formation of a step defined by the first opening 41 ofmask layer 40.

When etching progresses, material of the second insulating layer 32,which fills the first opening 41 of mask layer 40, will be removedtogether with material of the first insulating layer 31. As etching isselective with respect to the material of the mask layer 40, partiallyexposed mask layer 40 functions as etching mask for the first insulatinglayer 31. Hence, a first opening 31 a is formed in the first insulatinglayer 31. First opening 31 a is aligned with respect to the firstopening 41 of mask layer 40 and thus also with first doping region 21.

Alternatively, first opening 31 a of first insulating layer 31 can beetched before implantation. In a further alternative, first opening 31 acan be etched after implantation and before formation of the secondinsulating layer 32. In either case, mask layer 40 serves as etchingmask. According to an embodiment, first opening 31 a in the firstinsulating layer 31 is formed together with first opening 32 a of thesecond insulating layer 32 by a common etching process.

In a further process, a conductive material is deposited to form at lestone contact element 50. Contact element 50 is in electrical contact withthe first doping region 21 and extends from the surface of, and fills,the first doping region 21 through the first opening 31 a in the firstinsulating layer 31, through the first opening 41 in the mask layer 40and through the first opening 32 a in the second insulating layer 32.The contact element 50 is also in contact with the mask layer 40,particularly with the exposed portions adjacent to the first opening 41.

A contact area between the contact element 50 and the first dopingregion 21 is therefore also laterally aligned with first doping region21. The contact element 50 can be centred with respect to the firstdoping region 21. This is beneficial for example when considering abipolar transistor. First doping region 21 can form, for example, theemitter of the bipolar transistor while contact element 50 can form anemitter contact. Since both are centred with respect to each other, theemitter efficiency is improved unlike devices formed by other processeswhich do not employ a self-adjusted formation of the emitter contactwith respect to the emitter. Self-adjusted formation is due to the useof mask layer 40, which forms an implantation mask for the first dopingregion 21 and an etching mask for etching the first insulating layer 31.

The self-aligned formation of the emitter contact and emitter maintainsthe emitter width and therefore improves the emitter efficiency.Furthermore, process variations are significantly reduced since both thefirst doping region 21 and the contact element 50 are aligned withrespect to each other irrespective of any misalignment between separatelithographical mask. As described above, mask layer 40 is the only maskused to define the location of first doping region 21 (for exampleemitter) and the contact element 50 (for example emitter contact).Misalignment between first doping region 21 and contact element 50 istherefore avoided. In other words, mask layer 40 is used to form aself-aligned contact opening with respect to the first doping region 21.

FIGS. 2A to 2C illustrate the layout design of planar bipolartransistors according to several embodiments. The upper illustrations ofFIGS. 2A to 2C show respective plan views onto the first surface 11 ofthe semiconductor substrate 10 while the lower illustrations of FIGS. 2Ato 2C show respective cross-sectional views along line AA′. For the sakeof illustration purposes only and not meant as limitation, FIGS. 2A to2C show pnp-bipolar transistors. All details given herein also apply tonpn-bipolar transistors.

FIG. 2A illustrates a lateral pnp-bipolar transistor having arotationally symmetric layout. A circular emitter region 21 is formed ina central region of the bipolar transistor surrounded by a rotationallysymmetric p-doped collector 22. P-doped collector 22 and p-doped emitter21 are laterally spaced apart from each other by n-doped base region 25which is formed by n-doped epitaxial region 14 arranged on p-doped wafer15. N-doped Epitaxial region 14 and p-doped wafer 15 together formsemiconductor substrate 10. Base region 25 is contacted through buriedn-doped region 23 and n-doped region 24 which is also referred to as“n-sinker”. The bipolar transistor is laterally surrounded by p-dopeddevice isolation 26 which extends up to the p-doped wafer 15.

Lateral bipolar transistors do not have to be circular-rotationallysymmetric as illustrated in FIG. 2A, but can have other layout designsas well. FIG. 2B illustrates a rotationally symmetric design(rotationally symmetric with respect to a rotation of about 90°) with acentral emitter 21 having a quadratic shape surrounded by collector 22.Hence, collector region 22 forming a second doping region laterallysurrounds, in a plan view onto the first surface of the semiconductorsubstrate 10, emitter region 21 forming a first doping region.

FIG. 2C illustrates a lateral bipolar transistor having a bar-shapedemitter 21 and a bar-shaped collector 22 spaced apart from emitter 21. Askilled person will appreciate that lateral pnp-transistors can havedifferent layouts which may be selected according to specific needs.

With respect to FIGS. 3A to 3E a further embodiment of a method formanufacturing a semiconductor device having a lateral pnp-transistor isdescribed. Similar as described in connection with FIGS. 1A to 1C, asemiconductor substrate 10 such as a silicon substrate is providedhaving a first surface 11 and a second surface 12. Semiconductorsubstrate 10 includes a p-doped wafer 15 forming the second surface 12and an n-doped epitaxial layer 14 forming the first surface 11 of thesemiconductor substrate 10. N-doped buried region 23 is formed at theinterface (pn-junction) between p-doped wafer 15 and n-doped epitaxiallayer 14 and connected by n-sinker 24. P-doped device isolations 26laterally surround the region of the bipolar transistor.

In some embodiments, buried region 23 and sinker 24 are highly n-dopedwhile epitaxial layer 14 is lightly n-doped. Wafer 15 is lightly p-dopedwhile device isolations 26 are highly p-doped.

First insulating layer 31 is formed on the first surface 11 of thesemiconductor substrate 10, for example by thermal oxidation resultingin the formation of a silicon oxide layer. Mask layer 40 is then form asdescribed above. Mask layer 40 includes a first opening 41 defining thelocation of a subsequently formed emitter region. Mask layer 40 alsoincludes a second opening 42 laterally spaced from first opening 41.Second opening 42 can surround the first opening 41 to obtain a bipolartransistor having a collector region surrounding the emitter region.Second opening 42 can be defined by mask layer 40 together with anauxiliary mask layer 45 having a large opening for exposing mask layer40. An “inner rim” of auxiliary mask layer 45 defines “outer edges” ofthe second opening while an “outer rim” of mask layer 40 defines “inneredges” of the second opening 42.

Alternatively, as illustrated in FIG. 4A, mask layer 40 can be usedwithout auxiliary mask layer 45. FIG. 4A shows that second opening 42 isformed in mask layer 40 only.

The second opening 42 defines the location of a second doping regionwhich will form the collector region. Collector region can surround theemitter region or can be laterally spaced from the emitter region.

Mask layer 40 can be comprised of a conductive material such as dopedpolysilicon. When using a conductive material for mask layer 40, firstinsulating layer 31 is used to insulate conductive mask layer 40 fromthe semiconductor substrate 10. When mask layer 40 is comprised of aninsulating material, first insulating layer 31 can be omitted.

Dopants are implanted into the semiconductor substrate 10 using masklayer 40 as an implantation mask. The first opening 41 of mask layer 40defines the location of emitter region 21 as illustrated in FIG. 3Bwhile second opening 42 defines the location of collector region 22.FIG. 3A uses a combined implantation mask formed by mask layer 40 andauxiliary mask layer 45 while FIG. 4A uses only mask layer 40 as animplantation mask. For example, when using a “lateral” layout design asillustrated in FIG. 2C, a combined implantation mask as shown in FIG. 3Bcan be used. When using a rotationally symmetric layout as illustratedin FIGS. 2A and 2B, no additional auxiliary mask layer is needed andmask layer 40 is only used. FIG. 4B illustrates the layout of mask layer40 used for forming the layout design of FIG. 2A with first opening 41being a central opening surrounded by a ring-shaped second opening 42which is separated from first opening 41 by a ring-shaped mask portion43 of mask layer 40.

First doping region 21 (emitter) and second doping region 22 (collector)are formed by a common implantation process as illustrated in FIG. 3C.The first and second doping regions 21, 22 are highly p-doped regions inthis embodiment. The implantation energy is selected such that thedopants do not penetrate mask layer 40 and auxiliary mask layer 45.

After removal of auxiliary mask layer 45 in the case of FIG. 3C, secondinsulating layer 32 is deposited. In the case of the processes asillustrated in FIGS. 4A to 4C, no mask removal step is included since noauxiliary mask layer 45 was used. Second insulating layer 32 can be madeof the same material as first insulating layer 31 to form an insulatinglayer embedding conductive mask layer 40. In FIG. 3C, the interfacebetween the first and second insulating layers 31, 32 is indicated by adashed line.

In a further process, etching mask 33 is formed on second insulatinglayer 32. Etching mask 33 includes a first opening 33 a arranged abovefirst opening 41 of the conductive mask layer 40. A second opening 33 bis formed above second doping region 22 while a third opening 33 c isformed above n-sinker 24. Second and third openings 33 b, 33 c, whichcan be referred to as contact openings, are arranged such that they arenot above portions of mask layer 40 when seen in a projection onto firstsurface 11. This is to ensure that the openings formed subsequently intothe first and second insulating layers 31, 32 do not cover or bordermask layer 40 so that the openings and the conductive material depositedin a later process are insulated from conductive mask layer 40.

First opening 33 a of etching mask 33 has a larger lateral width thanfirst opening 41 of mask layer 40 as described above to ensure that thefirst opening 41 is fully exposed and can function as an etching mask.

In a further process, second and first insulating layers 32, 31 areetched in a common etching process which is selective with respect tothe material of mask layer 40. First opening 32 a of second insulatinglayer 32 completely exposes first opening 41 of mask layer 40 whichdefines the location and size of the first opening 31 a of firstinsulating layer 31 as described above. Second opening 31 b, 32 b offirst and second insulating layers 31, 32 extend to second doping region22 while third opening 31 c, 32 c of first and second insulating layersextend to n-sinker 24. Second opening 31 b, 32 b and third opening 31 c,32 c of first and second insulating layers 31, 32 are laterally spacedfrom mask layer 40. The resulting structure is shown in FIG. 3D.

FIG. 3E illustrates the structure after removal of etching mask 33 anddeposition of a conductive material which forms a first contact element51 in the first opening 31 a, 32 a of first and second insulating layersand first opening 41 of mask layer 40. Due to the partially exposed masklayer 40 within first opening 32 a of second insulating layer 32, whichresults in the formation of a step, first contact element 51 makescontact to mask layer 40 not only on the sidewalls of first opening 41but also on the upper surface of mask layer 40. This improves theelectrical contact between the first contact element 51 and mask layer40.

First contact element 51 has therefore a lower portion having a smallerlateral extension than an upper portion with a step portion formedbetween the upper and lower portions. The lower portion is disposed inthe first insulating layer 31 and mask layer 40. The upper portion isdisposed in the second insulating layer 32. The first and secondinsulating layers 31, 32 embed mask layer 40. First contact element 51can also be referred to as a plug.

A second contact element 52 is formed in the second opening 31 b, 32 bof the first and second insulating layers 31, 32 and a third contactelement 53 is formed in the third opening 31 c, 32 c of the first andsecond insulating layers 31, 32. Second and third contact elements 52,53 have a column-like shape and do not include a step portion unlikefirst contact element 51 since mask layer 40 is spaced apart from thesecontact elements. Second and third contact elements 52, 53 can also bereferred to as plugs. First, second and third contact elements 51, 52,53 can be comprised of tungsten or other suitable conductivematerial(s).

In further processes, metallization regions 61, 62, 63 are formed onsecond insulating layer 32 as illustrated in FIG. 3F. Metallizationregion 61 is in electrical contact with the first contact element 51,metallization region 62 is in electrical contact with the second contactelement 52 while metallization region 63 is in electrical contact withthe third contact element 53. Metallization regions 61, 62, 63 can becomprised of aluminium or other suitable conductive material(s).

Alternatively, first, second and third contact elements 51, 52, 53 canbe formed together with first, second and third metallization regions.For example, aluminium can be sputtered to fill openings 33 a, 33 b, 33c and to form a metal layer on second insulating layer. The metal layeris subsequently structured to form metallization regions 61, 62, 63.

First contact element 51 is formed laterally centred with respect to thefirst doping region 21 unlike second and third contact elements 52, 53which do not need to be laterally centred with respect to their dopingregions 22 and 24, respectively.

FIGS. 4A to 4C show variations of the processes illustrated in FIGS. 3Ato 3F. Different to FIG. 3A. FIG. 4A employs a mask layer 40 having afirst opening 41 and a second opening 42 laterally spaced to the firstopening 41. Therefore, no auxiliary mask layer is needed. First opening41 defines the location of the first doping region 21 while secondopening defines the location of the second doping region 22 whichlaterally surrounds the first doping regions 21. Mask layer 40 is shownin a plan view in FIG. 4B as described above.

The remaining steps can be carried out as described in connection withFIGS. 3C to 3F. Since mask layer 40 covers the region of n-sinker aswell, an additional etching step can be added to remove mask layer 40from regions above n-sinker 24. As shown in FIG. 4C, first contactelement 51 is centred with respect to first doping region 21 e.g.forming the emitter. Moreover, first contact element 51 is in directcontact with mask layer 40. Second contact element 52 is insulated frommask layer 40 to prevent a short between first and second doping regions21, 22.

FIG. 5 illustrates a plan view of a local wiring of a semiconductordevice according to an embodiment. The local wiring includes first andsecond vias 71, 72. A portion 44 of a conductive mask layer electricallyconnects first and second vias 71, 72 which are further in electricalconnection with first and second metallization regions 61, 62.Conductive mask layer 44 crosses a metal line 65.

FIG. 6 illustrates a semiconductor device having two laterally spacedbipolar transistors 101, 102 and a local wiring formed between theemitter contacts of the bipolar transistors as shown in FIG. 5. Eachbipolar transistor 101, 102 includes a central first doping region 21forming an emitter region, a second doping region 22 forming a collectorregion which laterally surrounds emitter region 21, and a base region 25arranged between the emitter region 21 and the collector region 22. Eachbipolar transistor 101, 102 includes a first contact element 51 that iscentred with respect to the respective emitter region 21. Second andthird contact elements 52, 53 are not necessarily centred with respectto their respective doping regions. Each of the first contact elements51 are in electrical connection to a metallization region 61 formed onthe second insulating layer 32. Metallization regions 61 areelectrically connected with each other through respective vias 71, 72and portion 44 of a conductive mask layer 40. Portion 44 is insulatedfrom other portions of mask layer 40. Hence, mask layer 40 can also beused for forming a local wiring.

FIG. 6 illustrates that the electrical connection between the twoemitter contacts 51 includes metallization portions 61 and vias 71, 72.To increase the integration density, local wiring using portions ofconductive mask layer 40 can also be formed as described in connectionwith FIG. 7.

FIG. 6 also shows that first and second insulating layers 31, 32 canhave a direct contact with each other in regions outside of mask layer40, 44. Furthermore, first and second insulating layers 31, 32 can haveopenings which extend only through the first and second insulatinglayers 31, 32 and which are spaced apart from openings formed in masklayer 40. Contact elements 52, 53 are formed in these openings.

FIG. 7 shows a semiconductor device having two lateral bipolartransistors 111, 112. First and second bipolar transistors 111, 112substantially have the same arrangements as shown in FIG. 6 except thatthey are more closely arranged with respect to each other and that thereis one device isolation 26 formed between the adjacent bipolartransistors 111, 112. Alternatively, two device isolations 26, which canbe arranged more closely together than in FIG. 6, can be arrangedbetween the adjacent bipolar transistors 111, 112 Both transistors 111,112 include an emitter contact 51 which is centred with respect to anemitter region 21. Both emitter contacts 51 are in direct electricalcontact with conductive mask layer 40, a portion 44 of which extendsfrom contact element 51 of the first bipolar transistor 111 to contactelement 51 of the second bipolar transistor 112. Hence, an electricalconnection between the contact elements 51 is formed without additionalmetallization portions and vias. This allows reducing the space neededto cross metal line 65.

A skilled person will appreciate that the formation of a local wiringusing portion 44 of conductive mask layer 40 is not limited to lateralbipolar transistors but can be used for any device. Hence, the localwiring can include a first contact element 51 centred with respect to adoping region 21 and a second contact element 51 centred with respect toa further doping region 21. The doping regions 21 are laterally spacedfrom each other. The contact elements 51 extend through a conductivemask layer 40 which is embedded in an insulating layer. Embeddinginsulating layer can include a first insulating layer 31 below and asecond insulating layer 32 above conductive mask layer 40. First andsecond contact elements 51 include a lower portion extending through themask layer 40 and an upper portion formed above mask layer 40. A stepportion can be formed between the lower and upper portions. The lowerportion electrically contacts the respective doping region. Conductivemask layer 40 and contact elements 51 can be made of the same or ofdifferent materials. Typically, contact elements 51 are of a differentconductive material than conductive mask layer 40. For example, contactelements 51 can be made of a metal or metal silicide while conductivemask layer 40 can be made of polysilicon or metal silicide.

The above described local wiring is particularly useful in devices whichonly include one polysilicon level and one metallization level such aspower devices. The polysilicon “bridge” formed by portion 44 ofconductive mask layer 40 starts immediately at the respective device andparticularly at a contact element of a doping region of the device.

The local wiring as illustrated in FIG. 7 can be manufactured by formingthe first insulating layer 31 and the conductive mask layer 40.Conductive mask layer 40 includes at least two openings which are spacedapart from each other and which both can define the location ofrespective doping regions 21 which are spaced apart from each other inthe finished device. The doping regions 21 are formed using conductivemask layer 40 as an implantation mask. Second insulating layer 32 isformed on conductive mask layer 40 and etched to form at least twoopenings which completely expose the openings in the conductive masklayer 40. First insulating layer 31 is then etched using conductive masklayer 40 as an etching mask to obtain openings in the first insulatinglayer 31 which are centred with respect to the doping regions 21. Theopenings are filled with a conductive material such as metal to formcontact elements which are centred with respect to the doping regionsand which are in electrical connection with each other using conductivemask 40 as the electrical connection.

The contact element does not necessarily have to be centred with respectto a doping region as described above to serve as contact element of alocal wiring. A local wiring can therefore also include a conductivemask layer 40 having two spaced apart openings 41 and contact elements51 which extend through the openings 41 of the conductive mask layer 40.The contact elements 51 extend to laterally spaced doping regions 21.Furthermore, contact elements 51 can include a step portion betweenlower and upper portion as described above. The openings 41 ofconductive mask layer 40 are used to define the location of the contactelements 51, hence conductive mask layer 40 is used as an etching maskonly.

For manufacturing such a local wiring, a semiconductor substrate 10 withrespective first doping regions 21 spaced apart from each other can beprovided. Then, the first insulating layer 31, mask layer 40 and secondinsulating layer 32 are formed. Mask layer 40 includes a first openingand a second opening. The first opening is arranged above a first one ofthe first doping regions 21 while the second opening is arranged abovethe other doping region 21. Since mask layer 40 is formed afterproviding of the first doping regions 21, the first and second openingsof mask layer 40 are not aligned or centred with respect to the dopingregions. In further processes, second insulating layer 32 is etched asdescribed above to form first and second openings and to expose thefirst and second openings of mask layer 40 which functions as an etchinglayer when etching progresses to form first and second openings in thefirst insulating layer 31. The respective first doping regions 21 arethereby at least partially exposed. In further processes, contactelements 51 are formed in the respective openings. Each contact element51 provides an electrical connection to one of the first doping regions21 and the contact elements 51 are in electrical contact with mask layer40. Mask layer 40 can furthermore be used to form contact doping regionsin the first doping regions 21. The contact doping regions can have ahigher doping concentration than the first doping regions and aretypically of the same conductivity type as the first doping regions.Furthermore, the contact doping regions are centred with respect to theopenings of the mask layer 40. Formation of contact doping regions isexplained in more detail with respect to FIG. 8. Metallization regionsin contact with the contact elements 51 can be formed on secondinsulating layer 32 as described above. The above described local wiringcan be formed without additional process costs or only with minoradditional costs. Furthermore, the local wiring is space-saving whichallows a higher integration density.

FIG. 8 illustrates a further embodiment of a semiconductor device havinga bipolar transistor. The bipolar transistor includes a first dopingregion 21 which forms here an emitter. The first doping region 21 can belightly p-doped and formed in an n-doped epitaxial layer 14 of asemiconductor substrate 10. Epitaxial layer 14 forms a doping area ofthe semiconductor substrate 10. A highly p-doped contact doping region27 is formed in the first doping region 21 at the first surface 11 ofthe semiconductor substrate 10. A first insulating layer 31, a masklayer 40, a second insulating layer 32 and a contact element 51 can beformed as described above. Contact element 51 is centred at least withrespect to contact doping region 27. Contact element 51 can also becentred with respect to doping region 21. When mask layer 40 is used asan implantation mask for the implantation of the first doping region 21and the contact doping region 27, both doping regions will be centredwith respect to the contact element 51.

The bipolar transistor of FIG. 8 is a high voltage device. To maintain ahigh blocking voltage, the emitter (first doping region 21) is onlylightly doped while contact doping region 27 is highly doped. Since aweekly doped emitter has a low efficiency, the highly doped contactdoping region 27 is provided. The location of contact doping region 27determines the emitter performance. Therefore, contact doping region 27is centred with respect to contact element 51. First doping region 21does not need to be centred with contact element 51. Contact dopingregion 27 also provides a low ohmic contact to the contact element 51.Contact doping region 27 therefore also improves the gain of the bipolartransistor.

The bipolar transistor further includes a second doping region 22forming a collector region 22 which is also weakly doped to maintain ahigh blocking voltage.

The bipolar transistor of FIG. 8 can be manufactured in a similar manneras described above. Mask layer 40 can be used for two implantations,namely the implantation of emitter region 21 and contact doping region27. Contact doping regions in the collector regions can be formed usingmask layer 40. Alternatively, contact doping regions in the collectorregions can be formed using an auxiliary mask. Furthermore, emitter andcollector regions 21, 22 can be implanted by a first implantation usingan auxiliary mask as implantation mask which is removed before masklayer 40 is formed for implanting contact doping region 27.

According to one or more embodiments, a method for manufacturing asemiconductor device is provided. The method includes providing asemiconductor substrate comprising a first surface; forming a firstinsulating layer on the first surface of the semiconductor substrate;forming a mask layer having a first opening on the first insulatinglayer, the first opening of the mask layer defining a location of afirst doping region; performing a first implantation step using the masklayer as implantation mask to form the first doping region in thesemiconductor substrate; etching the first insulating layer selectivelywith respect to the mask layer to expose a portion of the first dopingregion by forming a first opening in the first insulating layer usingthe mask layer as etching mask; and depositing a conductive material toform at least one contact element disposed in the first opening of thefirst insulating layer and in the first opening of the mask layer, thecontact element being in contact with the first doping region and themask layer.

According to one or more embodiments, a semiconductor device isprovided. The semiconductor device includes a semiconductor substratehaving a first surface and a first doping region. A first insulatinglayer having a first opening is disposed on the first surface of thesemiconductor substrate, wherein the first opening is arranged above thefirst doping region. A mask layer is disposed on the first insulatinglayer and includes a first opening, wherein the first opening in thefirst insulating layer and the first opening in the mask layer arelaterally centred with respect to the first doping region. At least afirst contact element is arranged in the first opening of the mask layerand the first opening of the first insulating layer. The first contactelement electrically connects the first doping region with the masklayer.

According to one or more embodiments, a method for manufacturing asemiconductor device is provided. The method includes providing asemiconductor substrate having a first surface, a first doping regionand a second doping region laterally spaced to the first doping region,a first insulating layer on the first surface of the semiconductorsubstrate, and a conductive mask layer having at least a first openingand a second opening spaced apart from the first opening on the firstinsulating layer, the first opening of the conductive mask layer beingarranged above the first doping region and the second opening of theconductive mask layer being arranged above the second doping region;etching the first insulating layer using the conductive mask layer asetching mask to by form a first and a second opening in the firstinsulating layer for exposing at least a respective portion of the firstand second doping region; and depositing a conductive material to form afirst contact element disposed in the first opening of the firstinsulating layer and the first opening of the conductive mask layer, anda second contact element disposed in the second opening of the firstinsulating layer and the second opening of the conductive mask layer,the first contact element being in electrical contact with the firstdoping region and the conductive mask layer, and the second contactelement being in electrical contact with the second doping region andthe conductive mask layer.

According to one or more embodiments, a semiconductor device isprovided. The semiconductor device includes a semiconductor substratehaving a first surface, a first doping region and a second doping regionlaterally spaced apart from the first doping region. A first insulatinglayer is arranged on the first surface of the semiconductor substrateand includes a first opening and a second opening. A conductive masklayer is disposed on the first insulating layer and has a first openingand a second opening, wherein the first opening of the conductive masklayer is arranged above the first opening of the first insulating layerand the second opening of the conductive mask layer is arranged abovethe second opening of the first insulating layer. A first contactelement is disposed in the first opening of the first insulating layerand the first opening of the conductive mask layer, and a second contactelement is disposed in the second opening of the first insulating layerand the second opening of the conductive mask layer, wherein the firstcontact element is in electrical contact with the first doping regionand with the conductive mask layer, and the second contact element is inelectrical contact with the second doping region and with the conductivemask layer.

According to one or more embodiments, a semiconductor device isprovided. The semiconductor device includes a semiconductor substratehaving a first surface, a doping area of a first conductivity type, afirst doping region of the second conductivity type arranged in thedoping area of the semiconductor substrate, and a contact doping regionof the second conductivity type arranged in the first doping region atthe first surface, wherein the contact doping region has a higher dopingconcentration than the first doping region. A first insulating layer isdisposed on the first surface of the semiconductor substrate, whereinthe first insulating layer includes a first opening above the contactdoping region. A mask layer is disposed on the first insulating layerand includes a first opening, wherein the first opening in the firstinsulating layer and the first opening in the mask layer are laterallycentred with respect to the contact doping region. At least one contactelement is arranged in the first opening of the mask layer and in thefirst opening of the first insulating layer, wherein the contact elementelectrically connects the contact doping region with the mask layer.

According to one or more embodiments, a method for manufacturing asemiconductor device is provided. The method includes providing asemiconductor substrate comprising a first surface; forming an emitterregion in the semiconductor substrate; forming a first insulating layeron the first surface of the semiconductor substrate; forming a masklayer comprising a first opening on the first insulating layer, thefirst opening of the mask layer defining a location of an emittercontact region; performing a first implantation step using the masklayer as implantation mask to form the emitter contact region in theemitter region of the semiconductor substrate; forming a secondinsulating layer on the mask layer to cover the first opening in themask layer, the material of the first and second insulating layers beingselectively etchable with respect to the material of the mask layer;forming an etching mask on the second insulating layer for defining atleast a first opening in the second insulating layer above the firstopening of the mask layer; etching the second insulating layerselectively with respect to the etching mask and the mask layer to formthe first opening in the second insulating layer, the first opening ofthe second insulating layer exposing the first opening in the masklayer; etching the first insulating layer selectively with respect tothe mask layer to expose a portion of the emitter contact region byforming a first opening in the first insulating layer using the masklayer as etching mask; depositing a conductive material to form at leastone contact element disposed in the first opening formed the firstinsulating layer, the first opening formed in the second insulatinglayer and the first opening formed in the mask layer, the contactelement being in contact with the emitter contact region and the masklayer.

Herein described are methods for manufacturing a semiconductor deviceaccording to several embodiments, particularly for manufacturing alateral bipolar transistor, which employs a conductive mask layer asimplantation mask and as etching mask for defining the location of acontact element relative to a doping region formed by implantation. Byso doing, adjustment tolerances are avoided and process variationsreduced. The conductive mask can be a polysilicon field plate. Thedoping region can form the emitter region while the contact element canform the emitter contact. An intermediate oxide can be deposited ontothe conductive mask layer and than etched. Conductive mask is therebypartially exposed and functions as etch mask. Hence, the thus formedcontact opening is aligned with respect to the emitter region. Themethod also allows formation of area-optimised wirings usingself-aligned contact elements and the conductive mask layer as localwiring between contact elements.

Features of the various exemplary embodiments described herein may becombined with each other, unless specifically noted otherwise.

Spatially relative terms such as “under”, “below”, “lower”, “over”,“upper” and the like, are used for ease of description to explain thepositioning of one element relative to a second element. These terms areintended to encompass different orientations of the device in additionto different orientations than those depicted in the figures. Further,terms such as “first”, “second”, and the like, are also used to describevarious elements, regions, sections, etc. and are also not intended tobe limiting. Like terms refer to like elements throughout thedescription.

As used herein, the terms “having”, “containing”, “including”,“comprising” and the like are open ended terms that indicate thepresence of stated elements or features, but do not preclude additionalelements or features. The articles “a”, “an” and “the” are intended toinclude the plural as well as the singular, unless the context clearlyindicates otherwise.

With the above range of variations and applications in mind, it shouldbe understood that the present invention is not limited by the foregoingdescription, nor is it limited by the accompanying drawings. Instead,the present invention is limited only by the following claims and theirlegal equivalents.

1-10. (canceled)
 11. A semiconductor device, comprising: a semiconductorsubstrate having a first surface and a first doping region; a firstinsulating layer on the first surface of the semiconductor substrate,the first insulating layer having a first opening arranged above thefirst doping region; a mask layer on the first insulating layer andhaving a first opening, the first opening in the first insulating layerand the first opening in the mask layer being laterally centred withrespect to the first doping region; a second insulating layer on themask layer and having a first opening above the first opening of themask layer; and at least a first contact element arranged in the firstopening of the second insulating layer, the first opening of the masklayer and the first opening of the first insulating layer, the firstcontact element electrically connecting the first doping region with themask layer.
 12. A semiconductor device according to claim 11, whereinthe semiconductor substrate further comprises a doping area of a firstconductivity type, wherein the first doping region is of a secondconductivity type and arranged in the doping area of the semiconductorsubstrate.
 13. A semiconductor device according to claim 11, wherein themask layer comprises an electrically conductive material.
 14. Asemiconductor device according to claim 13, wherein the contact elementcomprises a conductive material different than the conductive materialof the mask layer.
 15. A semiconductor device according to claim 11,wherein the semiconductor device is a first bipolar transistor and thefirst doping region forms an emitter region of the bipolar transistor.16. A semiconductor device according to claim 15, further comprising asecond bipolar transistor having an emitter region and a contact elementin electrical contact with the emitter region of the second bipolartransistor, wherein the mask layer electrically connects the firstcontact element of the first bipolar transistor with the contact elementof the second bipolar transistor.
 17. A semiconductor device accordingto claim 11, further comprising a contact doping region arranged in thefirst doping region, the contact doping region having the sameconductivity type as the first doping region and a higher dopingconcentration than the first doping region, the contact doping regionbeing laterally centred with respect to the mask layer.
 18. A method formanufacturing a semiconductor device, comprising: providing asemiconductor substrate having a first surface, a first doping regionand a second doping region laterally spaced from the first dopingregion, a first insulating layer on the first surface of thesemiconductor substrate, and a conductive mask layer having at least afirst opening and a second opening spaced apart from the first openingon the first insulating layer, the first opening of the conductive masklayer being arranged above the first doping region and the secondopening of the conductive mask layer being arranged above the seconddoping region; forming a second insulating layer on the conductive masklayer to cover the first and second openings in the conductive masklayer, the material of the first and second insulating layers beingselectively etchable with respect to the material of the conductive masklayer; forming an etching mask on the second insulating layer fordefining a first opening and a second opening of the second insulatinglayer; etching the second insulating layer selectively with respect tothe etching mask and the conductive mask layer to form the first openingand the second opening of the second insulating layer, the first openingof the second insulating layer exposing the first opening in theconductive mask layer and the second opening of the second insulatinglayer exposing the second opening in the conductive mask layer; etchingthe first insulating layer using the conductive mask layer as an etchingmask to form a first and a second opening in the first insulating layerfor exposing at least a respective portion of the first and seconddoping regions; and depositing a conductive material to form a firstcontact element disposed in the first opening formed in the firstinsulating layer, in the first opening formed in the second insulatinglayer and in the first opening formed in the conductive mask layer, anda second contact element disposed in the second opening formed in thefirst insulating layer, in the second opening formed in the secondinsulating layer and in the second opening formed in the conductive masklayer, the first contact element being in electrical contact with thefirst doping region and the conductive mask layer, and the secondcontact element being in electrical contact with the second dopingregion and the conductive mask layer.
 19. A method according to claim18, wherein the first opening in the conductive mask layer defines alocation of the first doping region, and the second opening in theconductive mask layer defines a location of the second opening; themethod further comprising: performing an implantation step using theconductive mask layer as an implantation mask to form the first dopingregion and the second doping region in the semiconductor substrate. 20.A method according to claim 18, further comprising: forming a firstmetallization region and a second metallization region spaced apart fromthe first metallization region on the second insulating layer, the firstmetallization region being in electrical contact with the first contactelement and the second metallization region being in electrical contactwith the second contact element.
 21. A semiconductor device, comprising:a semiconductor substrate having a first surface, a first doping regionand a second doping region laterally spaced apart from the first dopingregion; a first insulating layer on the first surface of thesemiconductor substrate and having a first opening and a second opening;a conductive mask layer on the first insulating layer and having a firstopening and a second opening, the first opening of the conductive masklayer being arranged above the first opening of the first insulatinglayer and the second opening of the conductive mask layer being arrangedabove the second opening of the first insulating layer; a secondinsulating layer on the conductive mask layer and having a first openingand a second opening, the first opening of the second insulating layerarranged above the first opening of the conductive mask layer, and thesecond opening of the second insulating layer arranged above the secondopening of the conductive mask layer; a first contact element disposedin the first opening of the first insulating layer, the first opening ofthe conductive mask layer and the first opening of the second insulatinglayer, the first contact element being in electrical contact with thefirst doping region and the conductive mask layer; and a second contactelement disposed in the second opening of the first insulating layer,the second opening of the conductive mask layer and the second openingof the second insulating layer, the second contact element being inelectrical contact with the second doping region and the conductive masklayer.
 22. A semiconductor device according to claim 21, furthercomprising: a first metallization region and a second metallizationregion spaced apart from the first metallization region on the secondinsulating layer, the first metallization region being in electricalcontact with the first contact element and the second metallizationregion being in electrical contact with the second contact element. 23.A semiconductor device according to claim 21, wherein the first dopingregion is laterally centred with respect to the first opening of theconductive mask layer and the second doping region is laterally centredwith respect to the second opening of the conductive mask layer.
 24. Asemiconductor device according to claim 21, wherein the first and secondinsulating layers are in contact with each other in regions outside ofthe conductive mask layer, the first and second insulating layers havinga third opening and a third contact element spaced apart from the firstand the second contact elements.
 25. A semiconductor device, comprising:a semiconductor substrate having a first surface, a doping area of afirst conductivity type, a first doping region of a second conductivitytype arranged in the doping area, and a contact doping region of thesecond conductivity type arranged in the first doping region at thefirst surface, the contact doping region having a higher dopingconcentration than the first doping region; a first insulating layer onthe first surface of the semiconductor substrate, the first insulatinglayer having a first opening above the contact doping region; a masklayer on the first insulating layer and having a first opening, thefirst opening in the first insulating layer and the first opening in themask layer being laterally centred with respect to the contact dopingregion; a second insulating layer on the mask layer and having a firstopening above the first opening of the mask layer; and at least onecontact element arranged in the first opening of the second insulatinglayer, in the first opening of the mask layer and in the first openingof the first insulating layer, the contact element electricallyconnecting the contact doping region with the mask layer.